Such a responder sends its message as soon as it receives a sufficient supply voltage for operation of its electronic circuit via its antenna. Moreover, since the responder is not initialised when the supply voltage is switched on, i.e. when the rectified voltage of the interrogation signal received by the responder reaches a value sufficient for operation of this responder, it starts to send a response signal commencing at a random position of the message contained in this response signal. It is provided that it repeats this message so that the reader ultimately receives a complete message by generally identifying the start of a message. Such a communication protocol therefore requires a relatively long communication period. This communication period can also be extended by pauses between the successive transmissions of the message, wherein such pauses are generally provided within the framework of an anti-collision protocol of the responses of several responders located in the field of emission of the same reader.
The operation of the responder of the type described above creates relatively long test times for the electronic circuits intended to form such responders. Such a test is generally conducted on a wafer comprising a high number of electronic circuits, wherein these circuits are tested simultaneously.
The test station applies needles to the two contact pads of each circuit intended to receive the two ends of a coil forming an antenna. In general, the test station supplies a signal corresponding to that of a reader and receives in return response signals from the circuits tested according to the communication protocol provided for the responders. The management of such a test is relatively complex for the test station that receives in parallel a very high number of response messages sent in a non-synchronised and repeated manner, in some cases after pauses of variable and sometime random duration. Therefore, the test requires a certain time to be reliable, and this increases the production cost of electronic circuits.
The aim of the invention is to provide an electronic circuit for the above-described type of responder but configured in order to allow a reliable and quick test of the integrated circuits to be conducted in a wafer, i.e. a batch test of a plurality of such circuits.
In this aim, the invention relates to an electronic circuit intended to form with an antenna a responder that operates without resetting to zero this electronic circuit (in other words, without resetting to the initial state or without the logic circuit being initialised) when the power supply of the electronic circuit is switched on, said electronic circuit comprising first and second contact pads respectively provided for the two ends of said antenna, a first extractor of a first clock signal connected electrically to the first contact pad and a logic circuit associated with a memory. This electronic circuit is firstly characterised in that it comprises a second extractor of a second clock signal electrically connected to the second contact pad and a generator of a zero reset signal of said logic circuit connected as input to the first and second extractors. According to a first embodiment, the electronic circuit is then characterised by the fact that the generator is configured to supply a zero reset signal to the logic circuit as soon as the difference between the number of pulses of the first clock signal and the number of pulses of the second clock signal is equal to or greater than a predefined positive integer. According to a second embodiment of the invention, the electronic circuit is then characterised by the fact that the generator is configured to supply a zero reset signal to the logic circuit as soon as this generator receives from the first extractor a predefined positive whole number of pulses without receiving a pulse from said second extractor during this reception.
According to particular variants, the generator is formed by a reversible counter or by an asynchronous counter, which outputs a signal corresponding to the state of the most significant or highest-order bit (MSB).
Because of the features of the electronic circuit according to the invention, the responder obtained after having connected an antenna to the electronic circuit operates without resetting to zero or initialisation when the supply voltage is switched on, since the electromagnetic signal received from a reader via the antenna of the responder is an alternative signal that creates the same number of pulses in the two extractors of a clock signal with a dual-cycle rectifier. If this number should not be identical in some circumstances, each extractor receives at least a clock pulse regularly. According to the second embodiment mentioned above, the generator of zero reset signals is itself reset to zero or initialised as soon as a pulse is supplied by one of the two given extractors, so that this generator will never supply a zero reset signal to the logic circuit when the corresponding responder receives an interrogation signal of any type from a reader. The difference in pulses of the two clock signals causing the reset to zero of the logic circuit is provided as sufficiently large, i.e. greater than any possible difference that can arise in particular cases, e.g. when the interrogation signal is modulated by a variation in phase or frequency.
Conversely, the circuit according to the invention allows a reset to zero or initialisation of the logic circuit by a test station. In fact, since the test is conducted with needles to establish an electrical connection for contact with the conductive pads of the circuit provided for the antenna, it is easy to supply independent signals to these two pads and to thus create different numbers of pulses in the clock signals supplied by the two clock extractors provided in the circuit according to the invention, which are respectively associated with these two pads.
It is possible in particular during the test to leave one of the two contact pads at a fixed potential so that no pulse is created in the extractor associated with this pad at least during the zero reset phase of the electronic circuits forming a tested wafer.